State-of-the-art mobile applications are characterized by small form factor, low cost, tight power budget, and high electrical performance. As the demand for smaller electronic products grows, manufacturers and others in the electronics industry continually seek ways to reduce the size of integrated circuits used in the electronic products. In that regard, three-dimensional type integrated circuit (3D IC) packaging techniques have been developed and used.
One packaging technique that has been developed is Package-on-Package (PoP). As the name implies, PoP is a semiconductor packaging innovation that involves stacking one package on top of another package. For a non-limiting example, a PoP device may combine vertically discrete memory and logic ball grid array (BGA) packages. One emerging PoP packaging technology is integrated fan-out Package-on-Package (InFO PoP). A plurality of dies are embedded in a material (such as molding compound), at two or more locations horizontally separated from each other. Interconnects between dies are formed in one or more redistribution layers above the dies. Using this technology, copper interconnects formed after the exposure of on-chip aluminum pads, known as post-passivation interconnects (PPI), allow signals to fan out to regions larger than the silicon die shadow. InFO PoP provides distinct advantages over conventional PoP that utilizes wire binding for connections between the packages. First, I/O's can be redistributed to the fan-out region outside of the silicon die footprint for increased pin count at the package level. Second, passive devices such as inductors and capacitors can be formed over the molding compound for lower substrate loss and higher electrical performance. Third, a smaller form factor leads to better thermal behavior and hence a lower operating temperature for the same power budget, or alternatively, faster circuit operation for the same temperature profile.